IGFET technology has become the favorite choice for those LSI applications where low cost is an overriding consideration. Relative to the expensive bipolar transistor technology, a lesser number of masking and processing steps are necessary to fabricate an array of interconnected IGFETs. This simplicity is partly due to the self-isolation feature of IGFETs not found in bipolars. In addition to reducing overhead costs, a low mask count implies a reduction of photolithographic operations and associated photo defects and thereby higher manufacturing yields are obtained. In short, there exists strong economic incentives to justify means reducing the mask count used for semiconductor wafer processing and, in particular, for IGFET fabrication. In connection with this, self-alignment features of a process reduce the area of device elements formed thereby since positioning tolerances are reduced. Device density also determines yield. As device density increases with a constant defect probability, yield per wafer increases. One way to increase device density is by having self-alignment between different regions of the device, a feature that naturally follows when a reduced number of masking steps is used in the definition of the device regions.
The most widely used IGFET processes of the prior art; aluminum and polysilicon gate, both use four masking steps in their simplest form. The aluminum gate process exemplifies well these steps: a first mask to define windows for source, drain and a first level interconnection pattern; a second mask to define gate and contact shapes; a third mask to open contacts and a fourth mask to pattern gate electrodes and a second metallized interconnection level.
A three-mask process has been proposed in the prior art by F. H. De La Moneda, "Three-Mask Self-Aligned IGFET Fabrication Process," U.S. Pat. No. 3,958,323, which eliminates the need for a contact opening mask by using two dielectric layers, one of which can be preferentially etched with respect to the other. It requires that the contact to the semiconductor substrate be made on the back side of the chip. Consequently, chips made by this process are not suitable for flip-chip packages which require that all contacts be on a single side. The three-mask process disclosed herein fabricates all contacts on a single side.